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E2E1026-27-Y4
Semiconductor MSM66101
Semiconductor OLMS-66K Series 16-Bit Microcontroller
This version: MSM66101 Jan. 1998 Previous version: Nov. 1996
GENERAL DESCRIPTION
The MSM66101 is a high performance microcontroller that employs OKI original nX-8/100 CPU core. This chip includes a 16-bit CPU, ROM, RAM, I/O ports, multifunction 16-bit timers, 10bit A/D converter, serial I/O port, and pulse width modulator (PWM).
FEATURES
* 64K address space for program memory * 64K address space for data memory * High-speed execution Minimum cycle for instruction * Powerful instruction set : : : : Internal ROM : 12K bytes Internal RAM : 384 bytes 400ns @ 10MHz Instruction set superior in orthogonal matrix 8/16-bit data transfer instructions 8/16-bit arithmetic instructions Multiplication and division operation instructions Bit manipulation instructions Bit logic instrucitons ROM table reference instructions Register addressing Page addressing Pointing register indirect addressing Stack addressing Immediate value addressing
* Abundant addressing modes
:
* I/O port Input-output port
5 ports 8 bits (Each bit can be assigned to input or output) Input port : 1 port 8 bits * Built-in multifunctional 16-bit timer :2 Following 4 modes can be set for each timer :Auto-reload timer mode Clock output mode Capture register mode Real time output mode * Serial port : 1 channel (UART mode with baud rate generator) * 12-bit pulse width modulator :2 * Watchdog timer * Transition detector :4 * 10-bit A/D converter : 8 channels * Interrupts Nonmaskable :1 Maskable : Internal 10/external 2 * Stand-by function STOP mode : Software clock stop mode HALT mode : Software CPU stop mode HOLD mode : Hardware CPU stop mode :
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MSM66101
* Package options: 64-pin plastic shrink DIP (SDIP64-P-750-1.78) : (Product name: MSM66101-SS) 64-pin plastic QFP (QFP64-P-1414-0.80-BK) : (Product name: MSM66101-GS-BK) 68-pin plastic QFJ (PLCC) (QFJ68-P-S950-1.27) : (Product name: MSM66101-JS) 64-pin ceramic piggyback (ADIP64-C-750-1.78) : (Product name: MSM66G101VS) * The piggyback type is used only for engineering samples. indicates the code number.
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P4.0/TM0CK P4.1/TM1CK P3.4/TM0IO SSP LRB
TIMER 0-1
P3.5/TM1IO EA READY ALE PSEN RD WR AD0/P0.0 AD7/P0.7 A8 /P1.0 ROM 12K 8 bits IR INSTRUCTION DEC. A15/P1.7
BLOCK DIAGRAM
Semiconductor
P3.1/RXD P3.0/TXD B U S PSW RAM 384 8 bits
SERIAL PORT
P4.4/TRNS0 P O R T
P4.7/TRNS3 MEMORY ALU CONT. PC RAP ALU ACC TEMPORARY R. CONSTANTS CONT.
TRANSITION D.
VREF P5.0/AI 0
P5.7/AI 7 AGND
A/D CONV.
C O N T .
P4.2/PWM0 P4.3/PWM1
PWM 0,1
NMI P3.2/INT0 P3.3/INT1
INTERRUPT CONT.
RESOUT P2.3/CLKOUT
PERIPHERAL CONT.
WDT
SYSTEM CONT.
PORT
GND VDD
FLT RES OSC1 OSC0
HLDA/P2.5 HOLD/P2.4
P0
P1
P2
P3
P4
P5
MSM66101
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MSM66101
PIN CONFIGURATION (TOP VIEW)
AD0/P0.0 AD1/P0.1 AD2/P0.2 AD3/P0.3 AD4/P0.4 AD5/P0.5 AD6/P0.6 AD7/P0.7 A8/P1.0 A9/P1.1 A10/P1.2 A11/P1.3 A12/P1.4 A13/P1.5 A14/P1.6 A15/P1.7 P2.0 P2.1 P2.2 CLKOUT/P2.3 RESOUT ALE PSEN RD WR READY EA FLT RES OSC0 OSC1 GND
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
VDD VREF AGND P5.7/AI7 P5.6/AI6 P5.5/AI5 P5.4/AI4 P5.3/AI3 P5.2/AI2 P5.1/AI1 P5.0/AI0 P4.7/TRNS3 P4.6/TRNS2 P4.5/TRNS1 P4.4/TRNS0 P4.3/PWM1 P4.2/PWM0 P4.1/TM1CK P4.0/TM0CK P3.7 P3.6 P3.5/TM1IO P3.4/TM0IO P3.3/INT1 P3.2/INT0 P3.1/RXD P3.0/TXD P2.7 P2.6 P2.5/HLDA P2.4/HOLD NMI
64-Pin Plastic Shrink DIP
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Semiconductor
PIN CONFIGURATION (TOP VIEW) (Continued)
A8/P1.0 A9/P1.1 A10/P1.2 A11/P1.3 A12/P1.4 A13/P1.5 A14/P1.6 A15/P1.7 P2.0
P2.1 10 P2.2 11
,
64 P0.7/AD7 63 P0.6/AD6 62 P0.5/AD5 61 P0.4/AD4 60 P0.3/AD3 59 P0.2/AD2
1 2 3 4 5 6 7 8 9
MSM66101
58 P0.1/AD1
57 P0.0/AD0
53 P5.7/AI7
52 P5.6/AI6
54 P5.5/AI5
50 P5.4/AI4
49 P5.3/AI3
48 P5.2/AI2 47 P5.1/AI1 46 P5.0/AI0 45 P4.7/TRNS3 44 P4.6/TRNS2 43 P4.5/TRNS1 42 P4.4/TRNS0 41 P4.3/PWM1 40 P4.2/PWM0 39 P4.1/TM1CK 38 P4.0/TM0CK 37 P3.7/TM3IO 36 P3.6/TM2IO 35 P3.5/TM1IO 34 P3.4/TM0IO 33 P3.3/INT1
CLKOUT/P2.3 12 RESOUT 13 ALE 14 PSEN 15 RD 16
WR 17
READY 18
EA 19
FLT 20
RES 21
OSC0 22
OSC1 23
GND 24
NMI 25
HOLD/P2.4 26
HLDA/P2.5 27
54 AGND
55 VREF
56 VDD
TXC/P2.6 28
RXC/P2.7 29
TXD/P3.0 30
RXD/P3.1 31
64-Pin Plastic QFP
INT0/P3.2 32
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MSM66101
PIN CONFIGURATION (TOP VIEW) (Continued)
52 P4.2/PWM0 51 P4.1/TM1CK
50 P4.0/TM0CK 49 NC
58 P5.0/AI0 57 P4.7/TRNS3
56 P4.6/TRNS2 55 P4.5/TRNS1
54 P4.4/TRNS0 53 P4.3/PWM1
46 P3.5/TM1IO 45 P3.4/TM0IO
AI3/P5.3 61 AI4/P5.4 62 AI5/P5.5 63 AI6/P5.6 64 AI7/P5.7 65 AGND 66 VREF 67 VDD 68
44 P3.3/INT1
60 P5.2/AI2 59 P5.1/AI1
48 P3.7 47 P3.6
43 P3.2/INT0 42 P3.1/RXD 41 P3.0/TXD 40 P2.7 39 P2.6 38 P2.5/HLDA 37 P2.4/HOLD 36 NMI 35 GND 34 GND 33 OSC1 32 OSC0 31 RES 30 FLT 29 EA 28 READY 27 WR
VDD 1 AD0/P0.0 2 AD1/P0.1 3 AD2/P0.2 4 AD3/P0.3 5 AD4/P0.4 6 AD5/P0.5 7 AD6/P0.6 8 AD7/P0.7 9
A8/P1.0 10 A9/P1.1 11
A10/P1.2 12 A11/P1.3 13
A12/P1.4 14 A13/P1.5 15
A14/P1.6 16 A15/P1.7 17
NC 18 P2.0 19
P2.1 20 P2.2 21
CLKOUT/P2.3 22 RESOUT 23
ALE 24 PSEN 25
NC: No-connection pin 68-Pin Plastic QFJ (PLCC)
RD 26
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MSM66101
PIN DESCRIPTIONS
Symbol P0.0-P0.7/ AD0-AD7 Type I/O Description P0: 8-bit input-output port. Each bit can be assigned to input or output. AD: Outputs the lower 8 bits of program counter during external program memory fetch, and receives the addressed instruction under the control of PSEN. Also outputs the address and outputs or inputs data during an external data memory access instruction under the control of ALE, RD, and WR. P1: 8-bit input-output port. Each bit can be assigned to input or output. A: Outputs the upper 8 bits of program counter (PC8-15) during external program memory fetch. Also this pin outputs the upper 8 bits of address during external data memory access instructions. I/O P2: 8-bit input-output port. Each bit can be assigned to input or output. CLKOUT: Output pin for supplying a clock to peripheral circuits. Output frequency range is equal to or twice the system clock. HOLD: Input pin to request the CPU to enter the hardware power-down state. HLDA: HOLD ACKNOWLEDGE: the HLDA signal appears in response to the HOLD signal and indicates that the CPU has entered the power-down state.
P1.0-P1.7/ A8-A15
I/O
P2.0-P2.2 P2.3/CLKOUT P2.4/HOLD P2.5/HLDA P2.6 P2.7 P3.0/TXD P3.1/RXD P3.2/INT0 P3.3/INT1 P3.4/TM0IO P3.5/TM1IO P3.6 P3.7
I/O
P3: 8-bit input-output port. Each bit can be assigned to be an input or an output. TXD: Serial port transmitter data output pin. RXD: Serial port receiver data input pin with high impedance. INT: Interrupt Request Input pin. TM0IO-TM1IO: One of the following signals is output or input. * Clock at twice the frequency range of the 16-bit timer overflow * Load trigger signal to the capture register input * Setting value output Whether the signal is input or output depends on the mode.
P4.0/TM0CK P4.1/TM1CK P4.2/PWM0 P4.3/PWM1 P4.4 - P4.7/ TRANS0 - 3 P5.0 - P5.7/ AI0 -AI7
I/O
P4: 8-bit input-output port. Each bit can be assigned to an input or an output. TM0CK, TM1CK: Clock input pins of timer 0, timer 1. TRANS: The input pins which sense the rising edge and set the flag. PWM: 12-bit pulse-width modulator output pin.
I
P5: 8-bit input port. AI: Analog signal input pin for A/D converter.
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MSM66101
PIN DESCRIPTIONS (Continued)
Symbol RESOUT ALE Type O O Description Outputs 'H' level when the CPU is in RESET status. Reset to 'L' level in some programs. Address Latch Enable: The timing pulse to latch the lower 8 bits of the address output from port 0 when the CPU accesses the external memory. The strobe pulse to fetch to external program memory.
PSEN RD WR READY EA FLT RES OSC0 OSC1 NMI VREF AGND VDD GND
O O O I I I I I O I I I I I
Program Store Enable:
Output strobe activated during a bus read cycle. Used to enable data on to the bus from the external data memory. Output strobe during a bus write cycle. Used as write strobe to external data memory. Used when the CPU accesses low speed peripherals. Normally set to 'H' level. If set to 'L' level, the CPU fetches the code from external program memory. If FLT is 'H' level, ALE, WR, RD, PSEN are set to 'H' level when reset. If FLT is set to 'L', ALE, WR, RD, PSEN are set to floating level when reset. RESET input pin. Clock oscillation pins Nonmaskable interrupt input pin (falling edge) Reference voltage input pin for A/D converter. Ground for A/D converter. System power supply. Ground.
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MSM66101
REGISTERS
Accumulator
15 ACC 0
Control Register (CR)
15 Program Status Word Program Counter Local Register Base System Stack Pointer PSW PC LRB SSP 0
Pointing Register (PR)
15 0
Index Register 1 Index Register 2 Data Pointer User Stack Pointer
X1 X2 DP USP
Local Register
7 ER0 ER1 ER2 ER3 R1 R3 R5 R7 07 R0 R2 R4 R6 0
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MSM66101
SFR
Address (HEX) 0000 0001 0002 0003 0004I 0005I 0006 0007 0010I 0011 0012I 0013 0018I 0019I 001AI 001BI 001CI 0020 0021 0022 0023 0024 0025 0026I 0028 0029 002AI 002C 002D 002E 002F 0030 0031 0032 0033 0034 0035 0036 0037 System stack pointer Local register base Program status word Accumulator Standby control register Watchdog timer Peripheral control register Stop code acceptor Interrupt request register Interrupt enable register External Iinterrupt control register Port 0 data register Port 0 mode register Port 1 data register Port 1 mode register Port 2 data register Port 2 mode register Port 2 secondary function control register Port 3 data register Port 3 mode register Port 3 secondary function control register Port 4 data register Port 4 mode register Port 4 secondary function control register Port 5 Timer 0 counter Timer 0 register Timer 1 counter Timer 1 register Name Symbol SSP (ASSP) LRB (ALRB)
PSWL (APSW)
R/W
8/16-bit Operation
Reset FFH FFH undefined
R/W
8/16
C8H 0CH 00H 00H F8H
PSWH ACC SBYCON WDT PRPHF STPACP IRQ 8/16 IE EXICON P0 P0IO P1 P1IO P2 P2IO P2SF P3 P3IO P3SF P4 P4IO P4SF P5 TM0 TMR0 R/W TM1 TMR1 16 R 8 R/W W R/W W 8
00H/WDT is stopped
FDH "0" 08H 0FH 08H 0FH FCH undefined 00H undefined 00H undefined 00H C7H undefined 00H C0H undefined 00H 00H -- 00H 00H 00H 00H 00H 00H 00H 00H
I indicates that the register has a nonexistent bit. 10/28
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MSM66101
SFR (Continued)
Address (HEX) 0040 0041 0046I 0048 0049 004AI 0050I 0051 0054 0055 0056I 0058I 0060I 0061 0062I 0063 0064I 0065 0066I 0067 0068I 0069 006AI 006B 006CI 006D 006EI 006F Name Timer 0 control register Timer 1 control register Transition detector register Serial port transmission baud rate generator counter Serial port transmission baud rate generator register Serial port transmission baud rate generator control register Serial port transmission mode control register Serial port transmission data buffer register Serial port receiving mode control register Serial port receiving data buffer register Serial port receiving error register A/D scan mode register A/D conversion result register 0 A/D conversion result register 1 A/D conversion result register 2 A/D conversion result register 3 A/D conversion result register 4 A/D conversion result register 5 A/D conversion result register 6 A/D conversion result register 7 Symbol TCON0 TCON1 TRNSIT STTM STTMR STTMC STCON STBUF SRCON SRBUF SRSTAT ADSCAN ADCR0 ADCR1 ADCR2 ADCR3 R ADCR4 ADCR5 ADCR6 ADCR7 8/16 undefined W R/W R R/W 8 R/W R/W 8/16-bit Operation Reset 00H 00H undefined 00H 00H 0FH 82H undefined 12H undefined F0H 80H
I indicates that the register has a nonexistent bit.
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MSM66101
SFR (Continued)
Address (HEX) 0070 0071I 0072 0073I 0074 0075I 0076 0077I 0078I 007AI Name PWM 0 counter PWM 0 register PWM 1 counter PWM 1 register PWM 0 control register PWM 1 countrol register Symbol PWMC0 PWMR0 8/16 PWMC1 PWMR1 PWCON0 PWCON1 8 R/W R/W 8/16-bit operation Reset 00H F0H 00H F0H 00H F0H 00H F0H 0CH 0CH
I indicates that the register has a nonexistent bit.
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MSM66101
ADDRESSING MODES
The MSM66101 provides independent 64K-byte data and 64K-byte program spaces with various types of addressing modes. These modes are shown below, for both RAM (for data space) and ROM (for program space). 1. RAM Addressing Mode (for data space) 1.1 Register Direct Addressing
Example ROR DP DP
1.2 Page Addressing a) Zero Page
Example L 0000H 0018H
A, 18H
SFR
b) Direct Page
Example ST xx00H xx10H
A,
off 10H
RAM
1.3 Pointing Register (PR) Indirect Addressing a) Data Point (DP) Indirect
Example SLL [DP] DP
RAM
b) User Stack Pointer (USP) Indirect
Example SRL 10H [USP] USP
-128 to +127
RAM
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MSM66101
c) Index Register (X1, X2) Indirect
Example INC 300H [X1] X1
0-65535
RAM
1.4 Immediate Addressing
Example MOV SSP, #27FH
2. ROM Addressing Mode (for program space) 2.1 Direct Addressing
Example LC A, 200H ROM 0200H
2.2 Simple Indirect Addressing
Example LC A, [DP] DP ROM
2.3 Double Indirect Addressing
Example LC A, [[DP]] RAM DP ROM
2.4 Indirect Addressing with 16-bit Offset
Example CMPC A, [300H [X1]] X1
0-65535
ROM
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Semiconductor
MSM66101
MEMORY MAPS
Program Memory Space
0000H 0000H
Internal ROM Area
0027H 0028H
Vector Table Area (40 bytes) VCAL Table Area (16 bytes)
0037H 0038H 2FFFH External Memory
FFFFH 2FFFH
Data Memory Space
0000H 007FH 0080H 00BFH 00C0H 00FFH 0000H SFR area PR area Special Function Registers PORT, A/D C, TIMER, PWM, etc.... 007FH 0080H PR0 PR1 PR2 PR3 PR4 PR5 PR6 PR7 00BFH 00C0H
Zero Page Area Internal RAM Area
80 82 84 86
X1 X2 DP USP
Low-Order High-Order
01FFH
External Memory Area
FFFFH
01FFH
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MSM66101
ABSOLUTE MAXIMUM RATINGS
(Ta = 25C) Parameter Supply Voltage Input Voltage Output Voltage Analog Ref. Voltage Analog Input Voltage Power Dissipation Symbol VDD VI VO VREF VAI 64-pin shrink DIP PD
Ta=85C per package
Condition
Rating -0.3 to 7.0 -0.3 to VDD+0.3
Unit
GND = AGND = 0V
-0.3 to VDD+0.3 -0.3 to VDD+0.3 -0.3 to VREF 930 565 1120 50 -55 to +150
V
64-pin QFP 68-pin QFJ
mW
Ta = 85C per output Storage Temperature TSTG --
C
RECOMMENDED OPERATING CONDITIONS
Parameter Supply Voltage Memory Hold Voltage Operating Frequency Ambient Temperature Fan Out Symbol VDD VDDH fOSC Ta N Condition fOSC 10MHz fOSC = 0Hz VDD = 5V 10% -- MOS load TTL load P0 P1, P2, P3, P4 Range 4.5 to 5.5 2.0 to 5.5 0 to 10 -40 to +85 20 2 1 -- Unit V MHz C
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Semiconductor
MSM66101
ELECTRICAL CHARACTERISTICS
DC Characteristics
(VDD = 5V 10%, Ta = -40 to +85C) Parameter "H" Input Voltage 1, 3, 6 "H" Input Voltage 5, 7 "H" Input Voltage 8 "H" Input Voltage 2 "L" Input Voltage 1, 2, 3, 6 "L" Input Voltage 5, 7 "L" Input Voltage 8 "H" Output Voltage 1, 4 "H" Output Voltage 2 "L" Output Voltage 1, 4 "L" Output Voltage 2 Input Leakage Current 3, 6, 7 Input Current 5 Input Current 8 "H" Output Current 1 "H" Output Current 2 "L" Output Current 1 "L" Output Current 2 Output Leakage Current 1, 2, 4 Input Capacitance Output Capacitance Analog Reference Power Supply Current Current Consumption (during STOP) * Current Consumption (during HALT) Current Consumption IOH VO = 2.4V IOL ILO CI CO IREF IDDS IDDH IDD VO = VDD/0V f = 1MHz Ta = 25C A/D in operation A/D stopped VDD = 2V -- fOSC = 10MHz No load IIH/IIL VI = VDD/0V VOH VOL IO = -400mA IO = -200mA IO = 3.2mA IO = 1.6mA VIL -- Symbol Condition Min. 2.4 4.0 4.2 3.6 -0.3 -0.3 -0.3 4.2 4.2 -- -- -- -- -- -2 -1 10 5 -- -- -- -- -- -- -- -- -- Typ. -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 5 7 0.3 0.5 0.2 1 6 20 Max. VDD+0.3 VDD+0.3 VDD+0.3 VDD+0.3 0.8 0.8 0.4 -- -- 0.4 0.4 1/-1 1/-20 10/-10 -- -- -- -- 2 -- -- 2 10 10 100 10 mA 35 mA pF mA mA mA mA mA V Unit
VIH
--
1: 2: 3: 4: 5: 6: 7: 8: *:
Applied to P0 Applied to P1, P2,P3 and P4 Applied to P5 Applied to ALE, PSEN, RD, WR and RESOUT Applied to RES and NMI Applied to READY and EA Applied to FLT Applied to OSC0 VDD or GND for ports serving as the input pin. No-load for any other.
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Semiconductor AC Characteristics * External program memory control
Parameter Clock (OSC) Pulse ALE Pulse Width PSEN Pulse Width PSEN Pulse Delay Time Low Address Setup time Low Address Hold Time High Address Delay Time High Address Hold Time Instruction Setup Time Instruction Hold Time Symbol tfW tAW tPW tPAD tAAS tAAH tAAD tAPH tIS tIH CL = 50pF Condition
--
MSM66101
(VDD=5V10%, Ta=-40 to +85C) Min. Max. Unit 50 3tfW-20 4tfW-20 tfW-20 2tfW-35 tfW-20 tfW-20 tfW-20 100 0
-- -- --
tfW+20 2tfW+20 tfW+40 tfW+40 tfW+40
--
ns
tfW-20
* External data memory control
Parameter Clock (OSC) Pulse ALE Pulse Width RD Pulse Width WR Pulse Width RD Pulse Delay Time WR Pulse Delay Time Low Address Setup Time Low Address Hold Time High Address Setup Time High Address Hold Time High Address Hold Time Memory Data Setup Time Memory Data Hold Time Data Delay Time Data Hold Time Symbol tfW tAW tRW tWW tRAD tWAD tAAS tAAH tAAD tARH tAWH tMS tMH tDD tDH CL = 50pF Condition
--
(VDD=5V10%, Ta=-40 to +85C) Min. Max. Unit 50 3tfW-20 4tfW-20 4tfW-20 tfW-20 tfW-20 2tfW-35 tfW-20 tfW-20 tfW-20 tfW-20 100 0 tfW-20 tfW-20
-- -- -- --
tfW+20 tfW+20 2tfW+20 tfW+40 tfW+40 tfW+40 tfW+40
--
ns
tfW-20 tfW+40 tfW+40
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Semiconductor
MSM66101
CLK tW ALE tAW PSEN tPAD tW
tPW INST0-7 tIS tIH
AD0-7
PC0-7 tAAS tAAH
AD8-15 tAAD RD tRAD
PC8-15 tAPH
tRW DIN 0-7 tMS tMH
AD0-7
RAP0-7 tAAS tAAH
AD8-15 tAAD WR tWAD
RAP8-15 tAPH
tWW DOUT0-7 tDH
AD0-7
RAP0-7 tAAS tAAH tDD RAP8-15 tAAD
AD8-15
tAWH
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Semiconductor * Serial port control Master mode
MSM66101
(VDD=5V10%, Ta=-40 to +85C) Parameter Clock (OSC) Pulse Width Serial Clock Pulse Width Output Data Setup Time Output Data Hold Time Input Data Setup Time Input Data Hold Time Symbol tfW tSCKW tSTMXS tSTMXH tSRMXS tSRMXH CL=50pF Condition -- -- Min. 50 8tfW 8tfW+40 6tfW-20 2tfW+10 50 Max. -- -- -- -- -- -- ns Unit
Slave mode
(VDD=5V10%, Ta=-40 to +85C) Parameter Clock (OSC) Pulse Width Serial Clock Pulse Width Output Data Setup Time Output Data Hold Time Input Data Setup Time Input Data Hold Time Symbol tfW tSCKW tSTSXS tSTSXH tSRSXS tSRSXH CL=50pF Condition -- -- Min. 50 8tfW 6tfW+40 6tfW-20 100 100 Max. -- -- -- -- -- -- ns Unit
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1 0 . & $ " 5 4 3 2 * ' H G K J I D C F E P O N V U T S R Q
Semiconductor MSM66101
OSC tW tW SCK tSCKW tSCKW SDOUT (TXD) tSTMXH tSTMXS SDIN (RXD) Valid Valid tSRMXH tSRMXS SCK tSCKW tSCKW SDOUT (TXD) tSTSXH tSTSXS SDIN (RXD) Valid Valid tSRSXH tSRSXS
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MSM66101
A/D Converter Characteristics
* Operating range
Parameter Power Supply Voltage Analog Reference Voltage Analog Input Voltage Analog Reference Power Voltage Resistance Operating Temperature Symbol VDD VR VAI RR Top VDD = 5V 10% VAG = GND = 0V Condition fOSC 10MHz Min. 4.5 4.5 VAG -- -40 Typ. -- -- -- 16 -- Max. 5.5 VDD VR -- +85 kW C V Unit
* A/D Converter accuracy Normal operation mode
Parameter Resolution Absolute Error Relative Error Zero Point Error Full Scale Error Differential Linearity Error Crosstalk Symbol n EA ER EZ EF ED EC Condition See the recommended circuit. VR=VDD VAG=GND=0V Analog input source impedance 5kW One channel conversion time tC=64ms -- -- -- 0 -0.5 -- -- (VDD=5V10%, fOSC=10MHz, Ta=-40 to +85C) Min. * -- -- -- 0 -1.0 -- -- -- -- -- -- -- -- 0.5 Typ. * -- -- -- -- -- -- 0.5 10
+3.0 -3.5
Max. * 10
+2.0 -3.5
Unit Bit
1.5 +3.0 -3.5 +3.0 --
1.0 +2.0 -3.5 +2.0 -- LSB
* VDD=5V, Ta=25C
HALT/HOLD operation mode
Parameter Resolution Absolute Error Relative Error Zero Point Error Full Scale Error Differential Linearity Error Crosstalk Symbol n EA ER EZ EF ED EC Condition See the recommended circuit. VR=VDD VAG=GND=0V Analog input source impedance 5kW One channel conversion time tC=64ms -- -- -- +0.5 -1.0 -- --
(VDD=5V10%, fOSC=10MHz, Ta=-40 to +85C) Min. * -- -- -- +0.5 -1.5 -- -- -- -- -- -- -- -- 0.5 Typ. * -- -- -- -- -- -- 0.5 10
+2.0 -3.5
Max. * 10
+1.0 -2.0
Unit Bit
1.0 +2.0 -3.5 +2.0 --
0.5 +1.0 -2.0 +1.0 -- LSB
* VDD=5V, Ta=25C
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Semiconductor * Recommended circuit
MSM66101
Reference Voltage + 0.1 47 F F
VREF
VDD + 0.1 47 F F
+5V
- + Analog Input
RI
AI0-7 GND 0.1 F AGND 0V
* A/D Converter conversion characteristics 1
Conversion Code
~
RI (Analog input source impedance) 5kW
[HEX] 3FF
EF MAX
EF MIN
Ideal Conversion (center line) Actual Conversion width
Actual Conversion (center line) 000
EZ MIN
EZ MAX
VREF Analog Input
[V]
Conversion Characteristics Diagram 1
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Semiconductor
MSM66101
Absolute error (EA) The absolute error indicates a difference between actual conversion and ideal conversion, excluding a quantizing error. The absolute error of the A/D converter gets larger as it approaches the zero point or full scale. (See to Conversion Characteristics Diagram 1.) Relative error (ER) The relative error indicates a deviation from a line which connects the center point of the zero point conversion width with that of the full scale conversion width, excluding a quantizing error. The relative error of this A/D converter is almost due to a differential linearity error. Zero point error (EZ) and full scale error (EF) The zero point error and full scale error indicate a difference between actual conversion and ideal conversion at the zero point and full scale, respectively. (See Conversion Characteristics Diagram 1.) * A/D Converter conversion characteristics 2 (Temperature Characteristics)
[HEX] 3FF -40C +85C
Conversion Code
[LSB] +25C +4
ES Differential Linearity Error +2
+3
ES +1 ES 000 Eta Analog Input [V] 0 -40
During normal operation During HALT +85 Temperature Ta [C]
Conversion Characteristics Diagram 2-1
Conversion Characteristics Diagram 2-2
Differential linearity error (ED) The differential linearity error indicates a difference between the actual conversion width (actual step width) and ideal value (1LSB). With this A/D converter, a voltage for actual conversion is shifted and the inclination of a voltage is changed, with changes of temperature (see Conversion Characteristics Diagram 2-1). Specifications described in the foregoing tables are established from Eta shown in Conversion Characteristics Diagram 2-1. Conversion Characteristics Diagram 2-2 shows temperature characteristics of differential linearity error of ES.
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Semiconductor
MSM66101
PACKAGE DIMENSIONS
(Unit : mm)
SDIP64-P-750-1.78
Package material Lead frame material Pin treatment Solder plate thickness Package weight (g)
Epoxy resin Cu alloy Solder plating 5 mm or more 8.70 TYP.
Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki's responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
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Semiconductor
MSM66101
(Unit : mm)
QFP64-P-1414-0.80-BK
Mirror finish
Package material Lead frame material Pin treatment Solder plate thickness Package weight (g)
Epoxy resin 42 alloy Solder plating 5 mm or more 0.87 TYP.
Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki's responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
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Semiconductor
MSM66101
(Unit : mm)
QFJ68-P-S950-1.27
Mirror finish
Package material Lead frame material Pin treatment Solder plate thickness Package weight (g)
Epoxy resin Cu alloy Solder plating 5 mm or more 4.50 TYP.
Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki's responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
27/28
Semiconductor
MSM66101
(Unit : mm)
ADIP64-C-750-1.78
Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki's responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
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